The formation of fine metallic features in close proximity to one another is of great commercial interest in several industries, most notably the printed circuit board (PCB), flexible circuit and packaging industries. The formation of smaller, more densely arranged components on the surface of a substrate allows the manufacture of PCB's that are cheap and operate quickly (due to the proximity of the components), and for flip chip applications the packaging industry requires the accurate patterning of solder bumps onto PCB's for connection to chips.
Many conventional methods of forming metallic features on substrates involve the use of photolithography to define a pattern on the substrate. However, this technique is cumbersome and expensive, and the size the of metallic features that can be produced thereby on, for example, PCB's is limited to around 30 μm and above. Moreover, the controlled formation of three-dimensional features (i.e. those which are raised above the surface of the substrate) is difficult using such conventional methods.
More recent techniques comprise the application of catalytic particles to the surface of a substrate by a soft stamp, the particles being applied in a pattern which corresponds to the metallic features that are to be created on the surface of the substrate. Prior to stamping, the substrate must first be activated by oxidation and/or silanization in order to ensure the particles will adhere to it. During subsequent electroless plating of the substrate, metal will only plate to the substrate where catalytic particles have been deposited. In this manner, small-scale metallic surface features can be created.
However, one drawback of this process is that the depth of the metallic features is limited by the amount of metal that can be deposited on a region of a substrate containing catalytic particles before lateral spreading of the metal takes place. This clearly places an upper limit both on the density of surface features that can be created using this technique and on the minimum distance between any two features.
A further drawback of this technique is that the oxidation and silanization steps are lengthy. Furthermore, since these surface treatments form a very thin (nanometer-sized) active layer on the surface, any moulding or deformation of the substrate during the stamping process is not practical. This precludes using the existing method for moulding non-planar circuitry during the stamping process. The stamping process using the previously described technique is also slow.